NV-SRAM: A nonvolatile SRAM with backup ferroelectric capacitors

This paper demonstrates new circuit technologies that enable a 0.25-mum ASI C SRAM macro to be nonvolatile with only a 17% cell-area overhead. New capa citor-on-metal/via-stacked-plug process technologies permit a nonvolatile S RAM (NV-SRAM) cell to consist of a six-transistor ASIC SRAM cell and two ba ckup ferroelectric capacitors stacked over the SRAM portion. READ and WRITE operations in this NV-SRAM cell are very similar to those of a standard SR AM, and this NV-SRAM shares almost all the circuit properties of a standard SRAM. Because each memory cell can perform STORE and RECALL individually, both can execute massive-parallel operations. A V-dd/2 plate-line architect ure makes READ/WRITE fatigue negligible. A 512-byte test chip was successfu lly fabricated to show compatibility with ASIC technologies.