Physical design guides for substrate noise reduction in CMOS digital circuits

Substrate noise injection in large-scale CMOS logic integrated circuits is quantitatively evaluated by 100-muV 100-ps resolution substrate noise measu rements of controlled substrate noises by a transition-controllable noise s ource and practical substrate noises under CMOS logic operations. The noise injection is dominated by leaks of supply/return bounce into the substrate , and the noise intensity is determined by logic transition activity, accor ding to experimental observations. A time-series divided parasitic capacita nce model is derived as an efficient estimator of the supply current for si mulating the substrate noise injection and can reproduce the measured subst rate noise waveforms. The efficacy of physical noise reduction techniques a t the layout and circuit levels is quantified and limitations are discussed in conjunction with the noise injection mechanisms. The reduced supply bou nce CMOS circuit is proposed as a universal noise reduction technique, and more than 90% noise reduction to conventional CMOS is demonstrated.