Direct digital frequency synthesis of low-jitter clocks

This paper presents a new phase correction technique applicable to phase ac cumulators that allows them to express arbitrary rational divide ratios suc h as R = N/M. Compared to existing methods, the technique gives better resu lts in terms of jitter, and it simplifies design and implementation of prac tical direct digital synthesis circuits. A typical application of the propo sed technique is digital television, where combinations of existing standar ds lead to the need to synchronize exactly a 6.144-MHz audio clock with a 3 5.46895-MHz video clock [1]. This implies a divide ratio of R = 122880/7093 79.