1.5-2.5 nm RTP gate oxides: process feasibility, properties and limitations

To support the international roadmaps' requirements, semiconductor manufact urers must develop new processing technologies, both to shrink the dimensio ns and to improve the performances of devices. As a consequence, gate oxida tion must advance to the 1.5-2.5 nm range over the coming years, to support the sub-0.18 mum technologies. We present here an overview of the more cri tical concern regarding this gate oxide downscaling. The limitations of rap id thermal processed (RTP) gate dielectric for oxide thickness <2 nm are di scussed in terms of process feasibility, oxide thickness determination and maximum gate leakage current. As a result, we show that oxides as thin as 1 .2 nm can be processed with control of the film uniformity (range within 0. 06 nm). However, we also demonstrate that the exponential increase of the g ate leakage current for oxides <2 nm does not allow integrating such thin d ielectric layers in present metal oxide semiconductor (MOS) devices (oxide thickness limit around 2.3 nm). (C) 2001 Elsevier Science B.V. All rights r eserved.