A novel on-chip electrostatic discharge protection design for RF ICs

A novel, compact electrostatic discharge (ESD) protection structure is desi gned, which protects integrated circuits (ICs) against ESD damages in ail m odes. This ultra-fast-response ESD structure, with response time of t(1) si milar to 0.16 nS, operates symmetrically. Measurements showed desired low h olding voltage (similar to2 V), low discharging impedance (<2<Omega>), high current handling capacity and adjustable triggering voltages. ESD testing passed HEM 14 and 15 kV air-gap IEC zapping. Design prediction was achieved by comprehensive mixed-mode ESD simulation. The area-efficient ESD design features small Si consumption, low parasitic effects and is particularly su itable for high-speed VLSI and RF ICs. The design was implemented in commer cial sub micron BiCMOS technologies for multi-power-supplies mixed-signal I Cs. (C) 2001 Elsevier Science Ltd. All rights reserved.