Designing nanometre silicon-on-insulator MOSFET with buried Si1-xGex quantum well channel

Citation
Y. Fu et al., Designing nanometre silicon-on-insulator MOSFET with buried Si1-xGex quantum well channel, PHYSICA E, 9(4), 2001, pp. 694-700
Citations number
14
Categorie Soggetti
Apllied Physucs/Condensed Matter/Materiales Science
Journal title
PHYSICA E
ISSN journal
13869477 → ACNP
Volume
9
Issue
4
Year of publication
2001
Pages
694 - 700
Database
ISI
SICI code
1386-9477(200104)9:4<694:DNSMWB>2.0.ZU;2-D
Abstract
We study the device characterization of Si-on-insulator (SOI) metal-oxide s emiconductor field effect transistor (MOSFET) with buried Si1-xGex quantum well (QW) channel. Accurate quantum mechanical description of the p-channel of the buried Si1-xGex QW shows that the peak carrier concentration in the conduction channel is higher in the positively graded SiGe QW, whereas the carriers are more uniformly distributed in the retrograded QW. By phenomen ologically introducing a physical parameter to describe the energy relaxati on of transmitting wave due to various scattering processes, systematic sim ulation about quantum wave transmissions of our SOI MOSFET indicates normal current-bias characteristics at nanometre regime. A threshold gate bias of about 0.6 V is obtained for both the positively graded and retrograded SiG e QWs. (C) 2001 Elsevier Science B.V. All rights reserved.