THE M-MACHINE MULTICOMPUTER

The M-Machine is an experimental multicomputer being developed to test architectural concepts motivated by the constraints of modern semicon ductor technology and the demands of programming systems. The M-Machin e computing nodes are connected with a 3-D mesh network; each node is a multithreaded processor incorporating 9 function units, on-chip cach e, and local memory. The multiple function units are used to exploit b oth instruction-level and thread-level parallelism. A user accessible message passing system yields fast communication and synchronization b etween nodes. Rapid access to remote memory is provided transparently to the user with a combination of hardware and software mechanisms. Th is paper presents the architecture of the M-Machine and describes how its mechanisms attempt to maximize both single thread performance and overall system throughput. The architecture is complete and the MAP ch ip, which will serve as the M-Machine processing node, is currently be ing implemented.