Low-voltage low-power CMOS full adder

Low-power design of VLSI circuits has been identified as a critical technol ogical need in recent years due to the high demand for portable consumer el ectronics products. In this regard many innovative designs for basic logic functions using pass transistors and transmission gates have appeared in th e literature recently. These designs relied on the intuition and cleverness of the designers, without involving formal design procedures. Hence. a for mal design procedure for realising a minimal transistor CMOS pass network X OR-XNOR cell, that is Fully compensated For threshold voltage drop in MOS t ransistors, is presented. This new cell can reliably operate within certain bounds when the power supply voltage is: scaled down, as long as due consi deration is given to the sizing of the MOS transistors during the initial d esign step. A low transistor count full adder cell using the new XOR-XNOR c ell is also presented.