Improved neuron MOS-transistor structures for integrated neural network circuits

The neuron MOS transistor is a recently discovered device which is capable of executing a weighted sum calculation of multiple input signals and thres hold operation based on the result of summation, thereby simulating the fun ction of biological neurons. A comprehensive set of neuron test transistors has been designed, where a number of input gates are coupled capacitively to a floating gate, which controls the channel current. integrated circuits for neural network applications have also been designed, based on the neur on MOS transistors, These circuits include neuron CMOS inverters and A/D an d D/A converters. To increase the accuracy of the neuron MOSFET structures, calibration techniques are proposed and tested. All the test structures an d circuits are implemented by using a standard 0.8 mum double-polysilicon C MOS technology. Attention was paid to saving of the layout area and reducin g power consumption.