Simulation is still the primary approach for the functional verification of
register-transfer level circuit descriptions written in hardware descripti
on language (HDL). The major problem of the simulation approach is to choos
e a good metric to gauge the quality of the test patterns. The finite state
machine (FSM) coverage test can find most of the design errors in a FSM. H
owever, it is impractical for large designs because of the state explosion
problem. In the paper, a higher-level FSM model is proposed to replace the
conventional FSM model in the coverage test. The state transition graph can
be significantly reduced in the model so that the complexity of the test s
ets becomes acceptable, even for large designs. This higher-level FSM model
, called the semantic finite state machine (SFSM) model, can be easily extr
acted from the original HDL code automatically with little computation over
head. The advantages of using this model instead of the conventional FSM mo
del in HDL design validation are thoroughly discussed. The implementation r
esults show that it is indeed a promising functional coverage metric.