Finite state machine encoding for VHDL synthesis

Finite state machine (FSM) optimisation has usually been studied through st ate assignment, state vector encoding, and combinational logic optimisation . Such details should not be consequential in behavioural descriptions. On the other hand, describing correct and efficient hardware structures in VHD L (VHSIC hardware description language), or generally in any high-level des cription language, is more a question of description style than correct lan guage statements. Therefore, more or less conscious choices are made in the design description itself that guide the synthesis software toward a speci fic implementation. The best implementation is also dependent on the target technology and therefore, there is no single best description style for al l FSMs. The paper is a study of the kind of performance trade-offs that can be made by changing the description style. A program is shown to be able t o generate these different descriptions from an intermediate format (kiss2) describing the FSM. Therefore, this process for finding a better descripti on could be automated and performed by the synthesis software itself. Descr iptions are tested on a set of 13 FSMs most from a benchmark suite LGSynth9 3. The results show at least two times better performance of speed or area in the best description compared with the worst. In performance critical ap plications this difference can be of a crucial importance.