A CMOS programmable analog memory-cell array using floating-gate circuits

Citation
Rr. Harrison et al., A CMOS programmable analog memory-cell array using floating-gate circuits, IEEE CIR-II, 48(1), 2001, pp. 4-11
Citations number
14
Categorie Soggetti
Eletrical & Eletronics Engineeing
Journal title
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-ANALOG AND DIGITAL SIGNAL PROCESSING
ISSN journal
10577130 → ACNP
Volume
48
Issue
1
Year of publication
2001
Pages
4 - 11
Database
ISI
SICI code
1057-7130(200101)48:1<4:ACPAMA>2.0.ZU;2-6
Abstract
The complexity of analog VLSI systems is often limited by the number of pin s on a chip rather than by the die area. Currently, many analog parameters and biases are stored off-chip. Moving parameter storage on-chip could save pins and allow us to create complex programmable analog systems. In this p aper, we present a design for an on-chip nonvolatile analog memory cell tha t can be configured in addressable arrays and programmed easily. We use flo ating-gate MOS transistors to store charge, and we use the processes of tun neling and hot-electron injection to program values. We have fabricated two versions of this design: one with an nFET injection mechanism and one with a pFET injection mechanism. With these designs, we achieve greater than 13 -bit output precision with a 39-dB power-supply rejection ratio and no cros stalk between memory cells.