A practical floating-gate Muller-C element using vMOS threshold gates

This paper presents the rationale for vMOS-based realizations of digital ci rcuits when logic design techniques based on threshold logic gates are used , Some practical problems in the vMOS implementation of threshold gates hav e been identified and solved. The feasibility and versatility of the propos ed technique as well as its potential as a low-cost design technique Tor CM OS technologies have been shown by experimental results from a multiple-inp ut Muller C-element, The proposed new realization exhibits better performan ce related to delay and area and power consumption than the traditional log ic implementation.