Imaging of the lateral GOI-defect distribution in silicon MOS wafers with lock-in IR-thermography

Yield and reliability of MOS devices are strongly affected by crystal-origi nated particles which may generate gate oxide integrity (GOI) defects. For the semiconductor industry it is highly desirable not only to measure the d ensity, but also to image the lateral distribution of GOI-defects. A novel technique to image GOI defects across large gate areas has been developed. First, a low-ohmic bias purse is used to break down nearly all GOI defects in a large-area MOS structure. Then a periodic bias of typically 2V is appl ied and the local temperature variation caused by the leakage current throu gh the broken GOI defects is imaged by lock-in IR-thermography. This techni que has been used to image the GOI defect distribution across 8 " Czochrals ki wafers. Various lateral variations of the defect distribution have been confirmed. (C) 2001 Elsevier Science Ltd. All rights reserved.