Influence of the polysilicon doping on the electrical duality of thin oxides: a confrontation between vertical and horizontal furnaces

In this work. the influence of polysilicon doping on thin oxides (thickness equal or below 10nm) quality and reliability (thickness equal or below 10 nm) in MOS capacitors with polysilicon gate is evaluated. By observing the polysilicon deposed in Vertical and horizontal furnaces, a higher degradati on in the oxide-silicon interface at high doping concentration has been fou nd. In the case of vertical furnaces, a more evident charge trapping in the constant current stress (CCS) V(t) curves and Qbd (ERCS) degradation have also been noticed. Resistivity measurements at different concentrations sho w a saturation effect just in correspondence of the oxide degradation. From a morphological point of view, the poly deposited in vertical furnaces con sists of grains which are larger than the ones found in horizontal furnace polysilicon and contains lower microdefectivity. Starling from these observ ations a model explaining the polysilicon morphology role in the oxide reli ability can be proposed. According to it, the degradation of the interface is caused by the phosphorus coming from the "in situ" doped polysilicon. Th e hypothesis is that, at high concentrations and in presence of very large polysilicon grains, phosphorous cannot segregate at the interfaces among th e polysilicon grains and, moving through the thin oxide, damages the silico n interface. This model has been confirmed by electrical, AFM and TEM analy sis and all the collected data have been related to the finished devices pe rformances (yield and reliability of CMOS flash memories, 0.25 mum technolo gy and below). (C) 2001 Elsevier Science Ltd. All rights reserved.