Prognostic methodology for deep submicron semiconductor failure modes

Semiconductor reliability issues are beginning to emerge as a major impedim ent to long term reliability of critical systems such as Internet routers, ATM machines, and Automotive/Aerospace fly-by-wire systems. Semiconductors have certain defined failure modes that can contribute to end-of-life failu res. These modes include time-dependent dielectric breakdown of the gate ox ide (TDDB), hot carrier damage, and metal migration. All of these common fa ilure modes are far worse at geometries below 0.25 u. Fortunately, there ar e methods proposed that counteract these common failure modes. This paper s urveys the problems involved, and recommends a methodology for the inclusio n of pre-calibrated prognostic cells that can be co-located with a host cir cuit to provide an "early-warning" of a system failure, so that appropriate corrective action can be taken.