Highly-parallel stereo vision VLSI processor based on arm optimal parallelmemory access scheme

Citation
M. Hariyama et al., Highly-parallel stereo vision VLSI processor based on arm optimal parallelmemory access scheme, IEICE TR EL, E84C(3), 2001, pp. 382-389
Citations number
8
Categorie Soggetti
Eletrical & Eletronics Engineeing
Journal title
IEICE TRANSACTIONS ON ELECTRONICS
ISSN journal
09168524 → ACNP
Volume
E84C
Issue
3
Year of publication
2001
Pages
382 - 389
Database
ISI
SICI code
0916-8524(200103)E84C:3<382:HSVVPB>2.0.ZU;2-L
Abstract
In a real-time vision system, parallel memory access is essential for highl y parallel image processing. The use of multiple memory modules is one effi cient technique for parallel access. In the technique; data stored in diffe rent memory modules carl be accessed in parallel. This paper presents an op timal memory allocation methodology to map data to be read in parallel onto different memory modules. Based on the methodology a high-performance VLSI processor for three-dimensional instrumentation is proposed.