A novel dynamically programmable arithmetic array (DPAA) processor for digital signal processing

A new architecture-based Dynamically Programmable Arithmetic Array processo r (DPAA) is proposed for general purpose Digital Signal Processing applicat ions. Paralielism and pipelining are achieved by using DPAA, which consists of various basic arithmetic blocks connected through a code-division multi ple access bus interface, The proposed architecture poses 100% interconnect ion flexibility because connections are done virtually through code matchin g instead of physical wire connections. Compared to conventional multiplexi ng architectures, the proposed interconnection topology consumes less chip area and thus, more arithmetic blocks can be incorporated. A 16-bit prototy pe chip incorporating 10 multipliers and 40 other arithmetic blocks had bee n implemented into a 4.5 mm x 4.5 mm chip with 0.6 mum CMOS process. DPAA a lso features its simple programmability, as numerical formula can be used t o configure the processor without programming languages or specialized CAD tools.