Comparison between standard and chain-type fram architectures

A standard 1T/1C and chain-type ferroelectric memory architecture are prese nted. The standard memory cell consists of a transistor connected in series to a ferroelectric capacitor while the chain-type cell connects these elem ents in parallel. Based on the different memory cells, two different arrays have been designed, simulated, and integrated on a single test chip in a 0 .35 mum process (not presented in this work). They are compared in regard t o area, performance, and reliability. It is shown that chain FRAM has the p otential to be superior to standard FRAM concerning area because of its inn ovative cell configuration which reduces the average number of lines per ro w from two to almost one and therefore removing the connectivity drawback r equired for bipolar polarization of ferroelectric materials compared to uni polar dielectric polarization. However, this obviously comes at the cost of limited performance and increased design complexity.