A read-disturb-free ferroelectric gate FET memory

The enhancement-type ferroelectric gate field-effect transistor (FeFET) req uires a read biasing voltage to the gate to secure a sufficient on/off curr ent ratio. However, disturb (depolarization) of the ferroelectric by repeti tive applications of read biasing voltage to the gate is a potential reliab ility concern. This paper deals with the disturb issue for an experimentall y fabricated FeFET with a stacked gate comprised of metal/SrBi2Ta2O9/CeO2. A significant difference between a high ON current and a low OFF current is brought about and sustained after a large number of read operations by cho osing a proper gate voltage, which is not only enough to make a positively programmed FeFET turn on, but also effective to prevent the disturb effect.