Optimization of Pt/SBT/CeO2/Si(100) gate stacks for low voltage ferroelectric field effect devices

MFIS (Metal Ferrorlectric Insulator Semiconductor) capacitors were fabricat ed on Si(100) substrate using CeO2 as the insulating buffer layer, SrBi2Ta2 O9(SBT) as the ferroelectric layer, and Pt as the top electrode material. X RD(T) analysis was used to examine the phase transition from the as-deposit ed, amorphous to the polycrystalline phase of the SET layer as a function o f the anneal temperature. The influence of the anneal temperature on the ca pacitance of MIS/MFIS structures and the memory window of MLIS capacitors w ill be discussed. To investigate the effect of interdiffusion between SET a nd CeO2, which can occur during the anneal process, Ce solution was added t o the SET solution before deposition. Pt/SBT/Pt and Pt/SBT(Ce)/Pt capacitor s fabricated with this solution were characterized.