Disturb free programming scheme for single transistor ferroelectric memoryarrays

Conventional AND and NOR non-volatile memory array circuits utilizing a sin gle ferroelectric memory field effect transistor (FEMFET) cell structure we re simulated by using a BSIM3v3 based FEMFET compact model. It is shown tha t the use of the common V-pp/2 and V-pp/3 rules for programming a transisto r in a FEMFET cell-array may cause the loss of stored information in adjace nt memory cells due to disturb pulses. To overcome this problem we propose to back-bias the substrate during the w rite cycle, which extends the depletion region of the FEMFET to higher gate -source voltages, and thus reduces the influence of a disturb pulse on the polarization of the gate ferroelectric. In addition we discuss device improvements which reduce the susceptibility to data loss without back-biasing the substrate in order to minimize cell a rea.