Avoiding exponential explosion: Generating compact verification conditions

Citation
C. Flanagan et Jb. Saxe, Avoiding exponential explosion: Generating compact verification conditions, ACM SIGPL N, 36(3), 2001, pp. 193-205
Citations number
15
Categorie Soggetti
Computer Science & Engineering
Journal title
ACM SIGPLAN NOTICES
ISSN journal
15232867 → ACNP
Volume
36
Issue
3
Year of publication
2001
Pages
193 - 205
Database
ISI
SICI code
1523-2867(200103)36:3<193:AEEGCV>2.0.ZU;2-3
Abstract
Current verification condition (VC) generation algorithms, such as weakest preconditions, yield a VC whose size may be exponential in the size of the code fragment being checked. This paper describes a two-stage VC generation algorithm that generates compact VCs whose size is worst-case quadratic in the size of the source fragment, and is close to linear in practice. This two-stage VC generation algorithm has been implemented as part of the Extended Static Checker for Java. It has allowed us to check large and comp lex methods that would otherwise be impossible to check due to time and spa ce constraints.