Simultaneous reference allocation in code generation for dual data memory bank ASIPs

We address the problem of code generation for DSP systems on a chip. In suc h systems, the amount of silicon devoted to program ROM is limited, so appl ication software must be sufficiently dense. Additionally, the software mus t be written so as to meet various highperformance constraints, which may i nclude hard real-time constraints. Unfortunately, current compiler technolo gy is unable to generate high-quality code for DSPs, whose architectures ar e highly irregular. Thus, designers often resort to programming application software in assembly-a time-consuming task. In this paper, we focus on providing support for one architectural feature of DSPs that makes code generation difficult, namely multiple data memory b anks. This feature increases memory bandwidth by permitting multiple data m emory accesses to occur in parallel when the referenced variables belong to different data memory banks and the registers involved conform to a strict set of conditions. We present an algorithm that attempts to maximize the b enefit of this architectural feature. While previous approaches have decoup led the phases of register allocation and memory bank assignment, thereby c ompromising code quality, our algorithm performs these two phases simultane ously. Experimental results demonstrate that our algorithm not only generat es high-quality compiled code, but also improves the quality of completely- referenced code.