FLOATING-BODY EFFECTS IN PARTIALLY DEPLETED SOI CMOS CIRCUITS

This paper presents a detailed study on the impact of floating body in partially depleted (PD) silicon-on-insulator (SOI) MOSFET's on variou s CMOS circuits. Digital very large scale integration (VLSI) CMOS circ uit families including static and dynamic CMOS logic, static cascade v oltage switch logic (static CVSL), dynamic cascade voltage switch logi c (dynamic CVSL) are investigated with particular emphasis on circuit topologies where the parasitic bipolar effect resulting from the float ing body manifests on the circuit operation and stability. Commonly us ed circuit building blocks for fast arithmetic operations in processor data-flow, such as static and dynamic carry lookahead circuits, and M anchester carry chains are examined. Pass-transistor-based designs inc luding latch, multiplexer, and pseudo two-phase dynamic logic are then discussed. It is shown that under certain circuit topologies and swit ching patterns, the parasitic bipolar effect causes extra power consum ption and degrades the noise margin and stability of the circuits. In certain dynamic circuits, the parasitic bipolar effect is shown to cau se logic state error if not properly accounted for.