A COMPREHENSIVE SUBMICROMETER MOST DELAY MODEL AND ITS APPLICATION TOCMOS BUFFERS

In this paper, an accurate delay model for MOS transistors in submicro meter CMOS digital circuits is presented. It takes into account a ramp shape input voltage anti a feed-forward capacitive coupling between g ate and drain nodes, along with the main second-order effects present in short-channel MOS transistors. The proposed model shows an average agreement with SPICE simulations of 3% the calculation of the propagat ion time, tested on a minimum inverter with a 0.7-mu m CMOS reference technology for a wide range of input voltage slopes. An example of app lication in optimization algorithms regarding CMOS tapered buffers is also reported. A maximum error ranging from 3-6% with respect to SPICE has been found for the optimized circuits.