A LOW-POWER CMOS ANALOG VECTOR QUANTIZER

We present a parallel analog vector quantizer (VQ) in 2.0-mu m double- poly CMOS technology and analyze its energetic efficiency. The prototy pe chip contains an array of 16 x 16 charge-based distance estimation cells, implementing a 16 analog input, 4-b coded output VQ with a mean absolute difference (MAD) distance metric. The distance cell includin g dynamic template storage measures 60 x 78 mu m(2). The output code i s produced by a 16-cell winner-take-all (WTA) output circuit of linear complexity which selects the winning template with constant power-del ay product, independent of input levels and scale. Experimental result s demonstrate 34 dB analog input dynamic range and 0.7 mW power dissip ation at 3 mu s cycle.