A 640-PS, 0.25-MU-M CMOS, 16X64-B 3-PORT REGISTER FILE

We describe a 640-ps read access, 16-word by 64-b, three-port register file fabricated in 0.25-mu m effective channel length CMOS technology , It features the capability to perform a write followed by a read in the same cycle at frequencies above 500 MHz. High speed is achieved by using a novel cell and array structure, Static circuit design is used exclusively throughout the entire register file and is optimized for high-speed operation, Measured results of the same-cycle read-after-wr ite demonstrate register file operations at 625 MHz, Additionally, int ernal probe measurements of the read access path components are presen ted and compared with circuit simulations.