GAAS PSEUDODYNAMIC LATCHED LOGIC FOR HIGH-PERFORMANCE PROCESSOR CORES

A novel GaAs logic family, pseudodynamic latched logic (PDLL), is pres ented in this paper, It is composed of a dynamic circuit where the log ic is performed and a static latch whose function is to permanently re fresh the stored data on a dynamic node, Because of this hybrid struct ure, PDLL takes advantage of both static and dynamic families and thus , permits implementation of very complex structures with good speed-ar ea-power tradeoff, Moreover, the inclusion of the latch permits this c lass of logic family to be highly efficient for pipelined systems work ing even at high temperature without loss of data due to leakage curre nts, Barrel-shifters, programmable logic arrays (PLA's), and carry loo kahead adders (CLA's) were verified by simulations demonstrating its f easibility for the development of high-performance very large scale in tegration (VLSI) systems.