3D integrated circuit layout visualization using VRML

This paper introduces the virtual reality modeling language (VRML) as a way to describe the layout of integrated circuits. Using this language, the ci rcuit can be viewed in three dimensions, adding the depth dimension, not pr esent in the regular layout description languages. A conversion tool that p arses 2D circuit layout descriptions and converts it into 3D VRML models is presented. A discussion about other applications of VRML on integrated cir cuits design and on educational tools is also included. (C) 2001 Elsevier S cience B.V. All rights reserved.