A 1-V 128-kb four-way set-associative CMOS cache memory using wordline-oriented tag-compare (WLOTC) structure with the content-addressable-memory (CAM) 10-transistor tag cell

This paper reports a 1-V 128-kb four-way set-associative CMOS cache memory implemented by a 0.18-mum CMOS technology using wordline-oriented tag-compa re (WLOTC) structure with the 10-transistor tag cell usually for content-ad dressable memory (CAM) for low-voltage low-power VLSI system application. O wing to the WLOTC structure with the CAM 10-transistor tag cell for accommo dating the one-step hit/miss generation and the dynamic pulse generators fo r realizing read-enable signals, a small hit access time (3.5 ns), low powe r consumption (4.1 mW at 50 MHz), and good expansion capability without sac rificing speed have been obtained.