On-chip ESD protection design by using polysilicon diodes in CMOS process

A novel on-chip electrostatic discharge (ESD) protection design by using po lysilicon diodes as the ESD clamp devices in CMOS process is first proposed in this paper, Different process splits have been experimentally evaluated to find the suitable doping concentration for optimizing the polysilicon d iodes for both on-chip ESD protection design and the application requiremen ts of the smart-card ICs. The secondary breakdown current (It2) of the poly silicon diodes under the forward- and reverse-bias conditions has been meas ured by the transmission-line-pulse (TLP) generator to investigate its ESD robustness, Moreover, by adding an efficient VDD-to-VSS clamp circuit into the IC, the human-body-model (HBM) ESD robustness of the IC with polysilico n diodes as the ESD clamp devices has been successfully improved from the o riginal similar to 300 V to become greater than or equal to3 kV, This desig n has been practically applied in a mass-production smart-card IC.