Speed and accuracy enhancement techniques for high-performance switched-current comparators

Design techniques for a high-performance switched-current (SI) comparator s uitable for low supply voltage operation is presented. To achieve accuracy and speed enhancement with minimum penalty to noise and power, two practica l schemes, namely the error-neutralization and double-regeneration techniqu es, are introduced. An experimental enhanced comparator achieves 9-bit reso lution at an operating speed of over 100 MHz and 2.5-V supply voltage while dissipating less than 2.1 mW. These results indicate an improvement in res olution of more than 2 bits and speed of more than 30% over those of a basi c SI comparator operating at the same power consumption.