LVDS I/O interface for Gb/s-per-pin operation in 0.35-mu m CMOS

This paper presents the design and the implementation of input/output (I/O) interface circuits for Gb/s-per-pin operation, fully compatible with low-v oltage differential signaling (LVDS) standard. Due to the differential tran smission technique and the low voltage swing, LVDS allows high transmission speeds and low power consumption at the same time, In the proposed transmi tter, the required tolerance on the de output levels was achieved over proc ess, temperature, and supply voltage variations with neither external compo nents nor trimming procedures, by means of a closed-loop control circuit an d an internal voltage reference. The proposed receiver implements a dual-ga in-stage folded-cascode architecture which allows a 1.2-Gb/s transmission s peed with the minimum common-mode and differential voltage at the input, Th e circuits were implemented in a 3.3-V 0.35-mum CMOS technology in a couple of test chips, Transmission operations up to 1.2 Gb/s with random data pat terns and up to 2 Gb/s in asynchronous mode were demonstrated. The transmit ter and receiver pad cells exhibit a power consumption of 43 and 33 mW, res pectively.