Techniques for widening lock and pull-in ranges and suppressing jitter in clock and data recovery ICs - Duplicated loop control CDR

This paper describes techniques for widening lock and pull-in ranges and su ppressing jitter in clock and data recovery ICs. It is shown theoretically that using a duplicated loop control (DLC)-phase-locked loop (PLL) techniqu e enables wider lock and pull-in ranges in clock and data recovery (CDR) wi thout increasing the cut-off frequency of the jitter transfer function. A 2 .5-Gb/s DLC-CDR IC fabricated with a 0.5-mum Si bipolar process provides 2. 5 times the lock range and 1.5 times the pull-in range of a conventional CD R IC, and the jitter characteristics of the fabricated CDR IC meet all thre e STM-16 jitter specifications in ITU-T recommendation G.958.