Hardware implementation of the high-dimensional discrete torus knot code

The hardware implementation of a proposed high dimensional discrete torus k not code was successfully realized on an ASIC chip. The code has: been work ed on for more than a decade since then at Aichi Prefectural University and Nagoya Institutes of Technology, both in Nagoya, Japan, [1]-[7]. The hardw are operation showed the ability to correct tile errors about five to ten t imes the burst length, compared to the conventional codes, as expected from tile code configuration and theory. The result in random error correction was also excellent, especially at a severely degraded error rate range of o rle hundredth to one tenth, and also for high grade characteristic exceedin g 10(-6) [3]-[5]. The operation was quite stable at the worst bit error rat e and realized a high speed up to 50 Mbps, since the coder-decoder configur ation consisted merely of an assemblage of parity check code and hardware c ircuitry with Ilo critical loop path. The hardware architecture has a uniqu e configuration and is suitable for large scale ASIC design. The developed code can be utilized for wider applications such as mobile computing and qu alified digital communications, since the code will be expected to work wel l in both degraded and high grade channel situations.