A smart photonic ATM switch architecture with compression strategy

Generally, the limitations of optical delay line and link capacity limit th e switching efficiency in the photonic asynchronous transfer mode (ATM) swi tch. Under the constraints, a smart photonic ATM switch designed for high-s peed optical backbone network should have some fast switching strategies so that the congestion can be avoided or reduced. In this paper, we will prop ose a novel smart photonic ATM switch architecture with a novel compression strategy, In the smart architecture, while more than two frames are destin ed for the same destination, the losers will be queued and compressed to re duce the degree of congestion. Therefore, not only the total switching time (TST) can be reduced but also the scarce buffer is able to store more inco ming cells. To meet the high-speed switching performance, a simple and effi cient compression derision algorithm (CDA) is proposed. The timing of emplo ying compression strategy and the saturated performance of proposed strateg y are analyzed, Simulation results show that compared to the conventional p hotonic ATM switch without compression strategy, the proposed strategy offe rs a much better performance in terms of queueing delay.