Simulations and measurements of capacitance in dielectric stacks and consequences for integration

In this paper simulations and measurements of capacitance in dielectric sta cks of dual damascene architecture are presented, and consequences for inte gration are discussed. Hard mask (HM) properties as thickness and relative permittivity (k) are taken into account together with the geometry of the d ual damascene architecture to study their influence on the effective permit tivity (k(eff)), RC delay and cross-talk resulting from the dielectric stac k. It is shown that a careful choice of the thickness and k-value of the ha rd masks is necessary to obtain an important decrease in k(eff). Decreasing the via height results in a small RC-delay increase but also in an importa nt cross-talk decrease. Finally, comparison between measured and simulated single damascene structures is reported. (C) 2001 Elsevier Science B.V. All rights reserved.