Advanced salicided 4 Mbit flash memory array with borderless contacts

System on chip development requires many different devices to be integrated on the same chip and a high compatibility between CMOS logic core process and added modules. The self-aligned silicide process coming from high perfo rmance logic gives in a Flash memory array several opportunities: to take a dvantage of low word-line resistance, to eliminate any metal strap in the a rray reducing potential process defectivity thus improving devices yield. O n the other hand, the salicidation of Flash memory requires at the same tim e to achieve a continuous low resistance Line on the no-flat array topograp hy (due to the double poly stacked gate memory cell structure) and to avoid any junction leakage risk, that might modify the device performances. The aim of this work is to demonstrate the feasibility and compatibility of adv anced Ti salicide process with Flash memory array embedded in a high perfor mance logic. The feasibility has been proven on a classical NOR 4 Mbit stan d-alone memory test chip processed in 0.25 mum technology, that furthermore asks for borderless contacts. (C) 2001 Elsevier Science B.V. All rights re served.