Solutions for the 100nm node with ultrathin silicon nitride gates

To continue the scaling trend of CMOS technology, the anticipated high gate leakage current in ultrathin gate dielectrics must be suppressed. In addit ion, dielectrics must also suppress boron diffusion and act as a barrier. A stack of oxide and nitride layers is an attractive replacement for the gat e dielectric. In this article, we present a gate dielectric composed of an oxide-on-nitride stack that provides two orders of magnitude lower leakage current than thermal oxide, minimal saturation current degradation, boron p enetration suppression, and improved reliability. Good wafer-to-wafer repea tability is demonstrated over a period of a few months.