Power optimization of technology-dependent circuits based on symbolic computation of logic implications

This paper presents a novel approach to the problem of optimizing combinati onal circuits for low power. The method is inspired by the fact that power analysis performed on a technology mapped network gives more realistic esti mates than it would at the technology-independent level. After each node's switching activity in the circuit is determined, high-power nodes are elimi nated through redundancy addition and removal. To do so, the nodes are sort ed according to their switching activity, they are considered one at a time , and learning is used to identify direct and indirect logic implications i nside the network. These logic implications are exploited to add gates and connections to the circuit; this may help in eliminating high-power dissipa ting nodes, thus reducing the total switching activity and power dissipatio n of the entire circuit. The process is iterative; each iteration starts wi th a different target node. The end result is a circuit with a decreased sw itching power. Besides the general optimization algorithm, we propose a new BDD-based method for computing satisfiability and observability implicatio ns in a logic network; furthermore, we present heuristic techniques to add and remove redundancy at the technology-dependent level, that is, restructu re the logic in selected places without destroying the topology of the mapp ed circuit. Experimental results show the effectiveness of the proposed tec hnique. On average, power is reduced by 34%, and up to a 64% reduction of p ower is possible, with a negligible increase in the circuit delay.