Allocation of FIFO structures in RTL data paths

Along with functional units, storage and interconnects contribute significa ntly to data path costs. This paper addresses the issue of reducing the cos ts of storage and interconnect. In a post-datapath synthesis phase, one or more queues can be allocated and variables bound to it, with the goal of re ducing storage and interconnect costs. Further, in contrast to earlier work , we support "irregular" cdfgs and multicycle functional units for queue sy nthesis. Initial results on HLS benchmark examples have been encouraging, and show t he potential of using queue synthesis to reduce datapath cost. A novel feat ure of our work is the formulation of the problem for a variety of FIFO str uctures with their own "queueing" criteria.