A novel SCR structure for on-chip ESD protection implemented with a deep su
bmicron triple well CMOS technology is presented. The triple well technolog
y offers the possibility of biasing the p-well, on which the structure is b
uilt, under transient ESD stress conditions and independently from the subs
trate. This greatly affects the turn on mechanism of the structure. Unlike
conventional SCR devices, the proposed p-well coupled SCR offers a reduced
triggering voltage level as well as the enhanced ESD performance of the SCR
devices. The turn on of this structure is realized with a common RC trigge
r network. The concept is supported by device simulation results.