SOI thermal impedance extraction methodology and its significance for circuit simulation

Citation
W. Jin et al., SOI thermal impedance extraction methodology and its significance for circuit simulation, IEEE DEVICE, 48(4), 2001, pp. 730-736
Citations number
9
Categorie Soggetti
Eletrical & Eletronics Engineeing
Journal title
IEEE TRANSACTIONS ON ELECTRON DEVICES
ISSN journal
00189383 → ACNP
Volume
48
Issue
4
Year of publication
2001
Pages
730 - 736
Database
ISI
SICI code
0018-9383(200104)48:4<730:STIEMA>2.0.ZU;2-W
Abstract
The buried-oxide in SOI MOSFET inhibits heat dissipation in the Si film and leads to increase in transistor temperature. This paper reports a simple a nd accurate characterization method for the self-heating effect (SHE) in SO I MOSFET. The ac output conductance at a chosen bias point is measured at s everal frequencies to determine the thermal resistance (R-th) and thermal c apacitance (C-th) associated with the SOI device. This methodology is impor tant to remove the misleadingly large self-heating effect from the de T-V d ata in device modeling. Not correcting for SHE mag lead to significant erro r in circuit simulation. After SHE is accounted for, the frequency-dependen t SHE may be disabled in circuit simulation without sacrificing the accurac y, thus providing faster circuit simulation for high-frequency circuits.