Device scaling limits of Si MOSFETs and their application dependencies

This paper presents the current state of understanding of the factors that limit the continued scaling of Si complementary metal-oxide-semiconductor ( CMOS) technology and prov ides an analysis of the ways in which application -related considerations enter into the determination of these limits. The p hysical origins of these limits are primarily in the tunneling currents. wh ich leak through the various barriers in a MOS field-effect transistor (MOS FET) when it becomes very small. and in the thermally generated subthreshol d currents. The dependence of these leakages on MOSFET geometry? and struct ure is discussed along with design criteria for minimizing short-channel ef fects and other issues related to scaling. Scaling limits due to these leak age currents arise from application constraints related to power consumptio n and circuit functionality. We describe her; these constraints work out fo r some of the most important application classes: dynamic random access mem ory (DRAM, static random access memory (SRAM), low-power portable det ices, and moderate and high-performance CMOS logic. As a summary: we provide a t able of our estimates of the scaling limits for various applications and de vice types. The end result is that there is no single end point for scaling . but that instead there are many end points, each optimally adapted to its particular applications.