Interconnect limits on gigascale integration (GSI) in the 21st century

Twenty-first century opportunities for GSI will be governed in part by a hi erarchy of physical limits on interconnects whose levels are codified as fu ndamental, material, device, circuit, and system. Fundamental limits are de rived from the basic axioms of electromagnetic, communication. and thermody namic theories, which immutably restrict interconnect performance, energy d issipation, and noise reduction, At the material level, the conductor resis tivity increases substantially in sub-50-nm technology due to scattering me chanisms that are controlled by quantum mechanical phenomena and structural /morphological effects. Ar the device and circuit level, interconnect scali ng significantly increases interconnect crosstalk and latency. Reverse scal ing of global interconnects causes inductance to influence on-chip intercon nect transients such that even with ideal return paths, mutual inductance i ncreases crosstalk by up to 60% over that predicted by conventional RC mode ls. Ar the system level, the number of metal levels explodes for highly con nected 2-D logic megacells that double in she every two years such that by 2014 the number is significantly larger than ITRS projections. This result emphasizes that changes in design, technology and architecture are needed t o cope with the onslaught of wiring demands. One potential solution is 3-D integration of transistors, which is expected to significantly improve inte rconnect performance. increasing the number of active layers, including the use of separate layers for repeaters, and optimizing the wiring network, y ields an improvement in interconnect performance of up to 145% at the 50-nm node.