Limitations and challenges of computer-aided design technology for CMOS VLSI

As manufacturing technology moves toward fundamental limits of silicon CMOS processing, the ability to reap the full( potential of available transisto rs and interconnect is increasingly important. Design technology (DT) is co ncerned with the automated or semi automated conception, synthesis, verific ation, and eventual testing of microelectronic systems. While manufacturing technology faces fundamental limits inherent in physical laws or material proper ties, design technology faces fundamental limitations inherent in th e computational intractability of design optimization and in the broad and unknown range of potential applications within various design processes. In this paper we explore limitations to how design technology can enable the implementation of single-chip microelectronic systems that take full advant age of manufacturing technology with respect to such criteria as layout den sity, performance. tmd power dissipation. One limitation is that the integr ated circuit (IC) design process-like an? other design process-involves pra ctical tradeoffs among multiple objectives. For example, there is a need to design correct and testable chips in a ver?; short time frame and for thes e chips to meet a competitive requirement. A second limitation is that the effectiveness of the design process is determined by its context-the design methodologies and flows we employ, and the designs that we essay-perhaps m ore than by its component tools and algorithms. If the methodology constrai ns the design in a particular way (e.g., row-based layout, or clocked-synch ronous timing), then even if individual tools all perform "optimally" it ma y be im possible to achieve an optimal result. On the other hand. without m ethodological constraints there are too many degrees of freedom for develop ers of design technology it adequately support the designer: A third limita tion is that while the design process as a whole seeks to optimize. the und erlying optimizations are computationally intractable. Hence, heuristic app roaches with few if any guarantees of solution quality must be ever-present within design technology This is perhaps the sole "fundamental limit" in d esign technology: Design technology by itself does not impose and fundamental limits on what can be implemented in silicon. And while "optimal use of silicon technology " is an ill-posed objective (going far beyond the scope of algorithms, tool s, methodologies, and infrastructure), design technology is the key to appr oaching and realizing the limits imposed by other aspects of the design pro cess. In this paper Lye summarize the mainstream methodologies used by CMOS silicon designers today and-against tile backdrop of international Technol ogy Roadmap for Semiconductors (ITRS) forecasts-point out basic limitations in their ability to achieve "optimal" design quality using reasonable reso urces. In each area of today's mainstream design flow: we either identify a nd quantify the factors limiting progress or point out the work that must b e done to obtain such an understanding. In particular; we emphasize the rol e of metrics in the design process and how ne might establish them. Finally we present a number of potential solutions to these problems in the form o f methodological approaches and major outstanding research questions that a re bring considered actively within the de sign technology research communi ty.