A QUEUE MANAGER CHIP FOR SHARED BUFFER ATM SWITCHES

This paper presents an efficient queue manager chip for controlling a 16 x 16 shared buffer ATM switch with a 256-cell buffer. Compared to c onventional implementations of queue managers for shared buffer ATM sw itches, our design eliminates the idle address FIFO and the pre-alloca ted bubbles at the tails of output queues. The former reduces the stor age size required for queue management, while the latter improves the effective buffer capacity. Such modular implementation also provides f lexibilities in queue management implementation. Backpressure with sof t-full and hard-full flow control for multi-stage expansion and two pr iority classes with push-out cell discarding are supported without ext ra hardware overhead. This chip was designed and fabricated using 0.8 mu m CMOS technology. It has 35,700 transistors in a chip area of 28.3 mm(2), with a core of 10.4 mm(2) and 31,960 transistors. Two test seq uences were developed during the design phase to fully verify the queu e management functions of the prototype chip. The queue manager chip w as tested up to 36 MHz, and is able to control a 16 x 16 shared buffer switch with a 155 MHz link rate.