VLSI-based processor arrays have been widely used for computation intensive
applications such as matrix and graph algorithms. Algorithm-based fault to
lerance designs employing Various encoding/decoding schemes have been propo
sed for such systems to effectively tolerate operation time fault. In this
paper, we propose an efficient algorithm-based fault tolerance design using
the weighted data-check relationship, where the checks are obtained from t
he weighted data. The relationship is systematically defined as a new (n, k
, N-w) Hamming checksum code, where n is the size of the code word, k is th
e number of information elements in the code word, and N-w is the number of
weights employed, respectively. The proposed design with various weights i
s evaluated in terms of time and hardware overhead as well as overflow prob
ability and round-off error. Two different schemes employing the (n, k, 2)
and (n, k, 3) Hamming checksum code are illustrated using important matrix
computations. Comparison with other schemes reveals that the (n, k, 3) Hamm
ing checksum scheme is very efficient, while the hardware overhead is small
.