Partial-response maximum-likelihood core development for a CD/DVD controller integrated circuit

A new PRML architecture is presented to demonstrate its superiority over th e conventional analog channel in a DVD system. In this new architecture, th e robustness to the baseline disturbance in the readback signal is emphasiz ed in developing the algorithms for the PLL, digital gain control, asymmetr y control, adaptive FIR filter, and Viterbi detector and post processor. In addition, a method of modeling the asymmetrical readback signal is discuss ed. A new algorithm for the digital PLL is described which does not require the oversampling. A simple method is presented to reduce the asymmetry in the ADC samples. To further improve the sensitivity to the baseline wanderi ng, a Viterbi detector is designed using the difference metric approach and followed by a post processor, which corrects the baseline related errors f rom the VD, A test chip is fabricated using 0.35 mum CMOS technology to dem onstrate the performance of the proposed architecture.